Integrated circuits, including computer chips, are manufactured by building up layers of circuits on the front side of silicon wafers. An extremely high degree of wafer flatness and layer flatness is required during the manufacturing process. Chemical mechanical planarization (CMP) is a process used during device manufacturing to flatten wafers and the layers built-up on wafers to the necessary degree of flatness.
Chemical mechanical planarization is a process involving polishing of a wafer with a polishing pad combined with the chemical and physical action of a slurry pumped onto the pad. The wafer is held by a wafer carrier, with the backside of the wafer facing the wafer carrier and the front side of the wafer facing a polishing pad. The polishing pad is held on a platen, which is usually disposed beneath the wafer carrier. Both the wafer carrier and the platen are rotated so that the polishing pad polishes the front side of the wafer. A slurry of selected chemicals and abrasives is pumped onto the pad to affect the desired type and amount of polishing. Using this process a thin layer of material is removed from the front side of the wafer or wafer layer. The layer may be a layer of oxide grown or deposited on the wafer or a layer of metal deposited on the wafer. The removal of the thin layer of material is accomplished so as to reduce surface variations on the wafer. Thus, the wafer and layers built-up on the wafer are very flat and/or uniform after the process is complete. Typically, more layers are added and the chemical mechanical planarization process repeated to build complete integrated circuit chips on the wafer surface.
As integrated circuit chips have become more complex, the standards of flatness and planarization necessary to create the integrated circuits and to achieve high yield in the process have become more and more stringent. At the same time, zones of differential response to the CMP process (due to the topography and underlying architecture of the particular integrated circuits built up on the wafer creates) and prime wafer height variations have become significant relative to the degree of flatness required for many processes in the manufacturing process. In prime wafers, high spots and low spots spanning millimeter-scale zones may be randomly located over the surface of wafer, and the height differential may be on the order of 100 nm. In processed wafers, high spots and low spots spanning millimeter-scale zones tend to be predictably and uniformly arrayed across the surface of the in-process wafer. The arrangement of high spots and/or low spots depends on the particular architecture of the built-up wafer, but is generally predictable from run to run, and it appears that the underlying architecture results in soft spots subject to an increase removal rate under CMP, or in hard spots that are resistant to removal of surface material. The excess wear leading to the low spots is referred to a dishing, and it is problematic because, among other reasons, it limits the resolution of lithography and creates high spots subject to thinning. (It may be appreciated that the terms soft-spot or hard-spot do not necessarily refer to the measured hardness of the wafer surface, and refer more generally to resistance or susceptibility to polishing).
The differential polishing described above differs from typical cross-wafer or center-to-edge differential polishing. Center-to-edge differential polishing describes the uniform over-polishing or under-polishing of the edge of the wafer compared to the center of the wafer. CMP processes have known inherent challenges in controlling center-to-edge uniformity. For example, oxide polishing is typically center-slow (the wafer's edge is polished faster than the wafer's center), while metal and prime wafer polishing are typically center-fast. Thus, annular zones of the wafer are polished differently.
The effects of uneven polishing have previously been addressed by adjusting the backpressure applied to different annular zones of wafer during polishing. The wafer is held against the polishing pad by a wafer carrier. The wafer carrier includes a pressure plate which is used to apply pressure on the back side of the wafer. For processes known to result in differential polishing rates, wafer carriers adapted to apply different backpressure to different zones of the wafer have been used. Pressure plates have been modified to provide for the application of different backpressure on the edge of the wafer and the center of the wafer, and in some cases a third concentric annular zone between the center and the edge. The current systems are useful in many processes. However, the soft-spot and hard-spot differential polishing identified above is not addressed by annular zoned backpressure systems, as the differential wear occurs over the entire surface of the wafer, and results in inconsistent polishing in all the annular zones.